NAND-memories are described in the publications of M. Ichige et al., “A novel self-aligned shallow trench isolation cell for 90 nm 4 Gbit NAND Flash EEPROMs” in 2003 Symposium on VLSI Technology Digest of Technical Papers, Session 7B-1; Y.-S. Yim et al., “70 nm NAND Flash Technology with 0.025 μm2 Cell Size for 4 Gb Flash Memory” in IEDM 2003, Session 34.1, 2003 IEEE Proceedings p. 819; D.-C. Kim et al., “A 2 Gb NAND Flash Memory with 0.044 μm2 Cell Size using 90 nm Flash Technology” in IEDM 2002, Session 37.1, 2002 IEEE Proceedings p. 919; and J.-D. Lee et al., “Data Retention Characteristics of Sub-100 nm NAND Flash Memory Cells” in IEEE Electron Device Letters, vol. 24, no. 12, December 2003, pp. 748–750. Each of these memory cells comprises a transistor body of semiconductor material, which is limited on two opposing sides by electrically insulating material of shallow trench isolations. An upper surface of the transistor body is planar and covered with a dielectric material, which is provided as tunnel oxide. Above the tunnel oxide, the floating gate electrode, comprising electrically conductive material, is arranged, which is surrounded by dielectric material and thus completely electrically insulated. A control gate electrode is arranged above the floating gate electrode and capacitively coupled to the floating gate electrode by an upper coupling dielectric between the electrodes.
The device comprising a planar upper surface of the transistor body has sharp edges confining the channel laterally in a direction that is orthogonal to the longitudinal channel direction running from source to drain. This gives rise to effects of a so-called corner device, the edges being designated as corners according to the usual cross-sections. Because of the sharp curvature of these edges, the electric field strength is much larger at the edges than in the middle part of the channel region. This results in a nonuniform current density along the channel width, which is larger at the transistor edges. Therefore, the devices show no proportionality between the current and the channel width. The transistor performance is also deteriorated by the variation of the field strength across the channel. A further disadvantage of this structure concerns the programming of the floating gate memory cells. A typical NOR device employs channel hot electron injection for programming and Fowler-Nordheim tunneling for erase. In typical NAND applications, both the programming and erasure are performed by Fowler-Nordheim tunneling. The tunnel currents are concentrated at the edges of the channel so that a thick tunnel oxide must be provided in order to achieve the required endurance of the device necessary for a large number of programming cycles.
In order to obviate these problems, floating gate memory cells having modified channel edges have been proposed. This is described, for example, in WO 01/41199 A1 on page 17. A better distribution of the electric field across the channel is obtained by a rounding or smoothing of the edges so that the electric field strength is decreased. As the upper surface of the transistor body deviates from the plane at the rounded edges, the tunnel oxide must be thicker in the marginal regions.
In these devices, the channel current increases approximately proportionally to the width of the channel, but the tunnel current of charge carriers passing across the tunnel oxide is restricted to a middle area of the channel, because the oxide layer in the marginal regions is too thick to be passed by tunneling charge carriers. Therefore, it is not necessary to provide a large general oxide thickness in order to inhibit a premature oxide damage at the channel edges sustaining the main programming current flow, but the lateral restriction of the tunnel area effects the endurance of the device negatively. This disadvantage originates from a higher current density during erase.
On the other hand, the requirements of reliability of the floating gate memory cell necessitates a minimal oxide thickness of typically about 7 to 8 nm, to ensure the desired data retention. Unfortunately, a further scaling down or miniaturization of the memory cell requires the application of a thinner tunnel oxide, as the relation of the thickness of the tunnel oxide and the channel length must be kept constant, in order to cope with the short-channel effects.